In a flash memory device, a memory cell has a floating gate or an insulating film called a charge storage layer, and data is stored by charging electrons in the charge storage layer. A silicon oxide nitride oxide silicon (SONOS) type structure of the flash memory device stores electrons in the nitride film in an oxide-nitride-oxide (ONO) film. For some time, a reduction of the size of the flash memory device has been a pressing issue. To scale down the memory cell, channel spacing between a source region and a drain region of the memory cell needs to be reduced. However, if the channel spacing is made small, spacing between charge storage regions which locally store electrons in the charge storage layer on both ends of the gate electrode of the memory cell also becomes small. Thereby, a phenomenon called a complementary bit disturb (CBD) occurs, where the charges stored in the charge storage regions interfere with each other. For example, charge or bit isolation between the two bits stored in two adjacent charge storage regions becomes increasingly difficult as the channel length is decreased. This may result in the bits from the two charge storage regions contaminating each other.
As for a NAND-type flash memory device, a method or a structure for suppressing the interference in the charge storage regions due to the CBD is proposed as in FIG. 1A and FIG. 1B. In FIG. 1A, a gate electrode 22 is formed on an oxide film 11 which is deposited above a semiconductor substrate 10. On both sides of the gate electrode 22, two charge storage layers 18 are separately formed within the oxide film 11. In the semiconductor substrate 10, diffusion regions 24, where each region serves as either a source region or a drain region, are formed. However, since the charge storage layers 18 are formed extended from the sides of the gate electrode 22, the structure may hinder the effort of scaling down the memory cell.
In FIG. 1B, on the semiconductor substrate 10, the oxide film 11 is formed between the gate electrode 22 and the semiconductor substrate 10. The two charge storage layers 18 are formed in the oxide film 11 separate from each other, with each charge storage layer 18 formed at each edge of the gate electrode 22. The diffusion regions 24 are formed in the semiconductor substrate 10. The structure described in FIG. 1B is effective in suppressing the effect of the CBD without sacrificing the real estate of the memory cell. However, aligning the gate electrode 22 and the charge storage layers 18 may be difficult since the separated charge storage layers 18 are formed before the gate electrode 22 is formed.